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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor adsp-bf592 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features up to 400 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and comp iler-friendly support advanced debug, trace, an d performance monitoring accepts a wide range of supply voltages for internal and i/o operations, see operating conditions on page 16 off-chip voltage regulator interface 64-lead (9 mm 9 mm) lfcsp package memory 68k bytes of core-accessible memory (see table 1 on page 3 for l1 and l3 memory size details) 64k byte l1 instruction rom flexible booting options from internal l1 rom and spi mem- ory or from host devices including spi, ppi, and uart memory management unit providing memory protection peripherals four 32-bit timers/counters, three with pwm support 2 dual-channel, full-duplex synchronous serial ports (sport), supporting eight stereo i 2 s channels 2 serial peripheral interface (spi) compatible ports 1 uart with irda support parallel peripheral interface (ppi), supporting itu-r 656 video data formats 2-wire interface (twi) controller 9 peripheral dmas 2 memory-to-memory dma channels event handler with 28 interrupt inputs 32 general-purpose i/os (gpios), with programmable hysteresis debug/jtag interface on-chip pll capable of frequency multiplication figure 1. processor block diagram sport0 voltage regulator interface port f jtag test and emulation peripheral access bus watchdog timer ppi spi0 spi1 boot rom dma access bus interrupt controller dma controller l1 data sram l1 instruction sram dcb b uart deb timer2C0 l1 instruction rom gpio sport1 twi port g
rev. b | page 2 of 44 | july 2013 adsp-bf592 table of contents features ................................................................. 1 memory ................................................................ 1 peripherals ............................................................. 1 general description ................................................. 3 portable low power architecture ............................. 3 system integration ................................................ 3 blackfin processor core .......................................... 3 memory architecture ............................................ 5 event handling .................................................... 5 dma controllers .................................................. 6 processor peripherals ............................................. 6 dynamic power management .................................. 8 voltage regulation ................................................ 9 clock signals ....................................................... 9 booting modes ................................................... 11 instruction set description ................................... 12 development tools ............................................. 12 additional information ........................................ 13 related signal chains ........................................... 13 signal descriptions ................................................. 14 specifications ........................................................ 16 operating conditions ........................................... 16 electrical characteristics ....................................... 18 absolute maximum ratings ................................... 20 esd sensitivity ................................................... 20 package information ............................................ 21 timing specifications ........................................... 22 output drive currents ......................................... 36 test conditions .................................................. 37 environmental conditions .................................... 40 64-lead lfcsp lead assignment ............................... 41 outline dimensions ................................................ 43 automotive products .............................................. 44 ordering guide ..................................................... 44 revision history 7/13rev. a to rev. b corrected processor block diagram ............................. 1 updated development tools .................................... 12 updated text in signal descriptions ............................ 14 corrected v ddint rating in table 14 , absolute maximum ratings ..................................... 20
adsp-bf592 rev. b | page 3 of 44 | july 2013 general description the adsp-bf592 processor is a member of the blackfin ? family of products, incorporating th e analog devices/intel micro signal architecture (msa). blackfin processors combine a dual- mac state-of-the-art signal proc essing engine, the advantages of a clean, orthogonal risc-lik e microprocessor instruction set, and single-instruction, multiple -data (simd) multimedia capa- bilities into a single in struction-set architecture. the adsp-bf592 processor is comp letely code compatible with other blackfin processors. the adsp-bf592 processor offers performance up to 400 mhz and reduced static power con- sumption. the processor features are shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next-generation applications that require risc-like program- mability, multimedia support , and leading- edge signal processing in one integrated package. portable low power architecture blackfin processors provide world-class power management and performance. they are prod uced with a low power and low voltage design methodology and feature on-chip dynamic power management, which provides the ability to vary both the voltage and frequency of operatio n to significantly lower overall power consumption. this capability can resu lt in a substantial reduction in power consumption, compared with just varying the frequency of operation. this allows longer battery life for portable appliances. system integration the adsp-bf592 processor is a hi ghly integrated system-on-a- chip solution for the next generation of digital communication and consumer multimedia applications. by combining industry standard interfaces with a high performance signal processing core, cost-effective applications can be developed quickly, with- out the need for costly exte rnal components. the system peripherals include a watchdog timer; three 32-bit tim- ers/counters with pwm support; two dual-channel, full-duplex synchronous serial ports (sports) ; two serial peripheral inter- face (spi) compatible ports; one uart ? with irda support; a parallel peripheral interface (ppi ); and a 2-wire interface (twi) controller. blackfin processor core as shown in figure 2 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-, 16-, or 32-bit da ta from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with cli pping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. the compare/select and vector search instructions are also provided. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). if the second alu is used, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction) and subroutine calls. hardware is pr ovided to support zero over table 1. processor features feature adsp-bf592 timer/counters with pwm 3 sports 2 spis 2 uart 1 parallel peripheral interface 1 twi 1 gpios 32 memory (bytes) l1 instruction sram 32k l1 instruction rom 64k l1 data sram 32k l1 scratchpad sram 4k l3 boot rom 4k maximum instruction rate 1 1 maximum instruction rate is not availabl e with every possible sclk selection. 400 mhz maximum system clock speed 100 mhz package options 64-lead lfcsp
rev. b | page 4 of 44 | july 2013 adsp-bf592 head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering) and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only . data memory holds data, and a dedicated scratchpad data memory stores stack and local vari- able information. multiple l1 memory blocks are provided. the memory management unit (mmu) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction inst ructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
adsp-bf592 rev. b | page 5 of 44 | july 2013 memory architecture the blackfin processor views memory as a single unified 4g byte address space, using 32- bit addresses. all resources, including internal memory and i/o control registers, occupy separate sections of this common address space. see figure 3 . the core-accessible l1 memory system is high performance internal memory that operates at the core clock frequency. the external bus interface unit (ebiu) provides access to the boot rom. the memory dma controller provides high bandwidth data- movement capability. it can perform block transfers of code or data between the l1 instruction sram and l1 data sram memory spaces. internal (core-accessible) memory the processor has three blocks of core-accessible memory, pro- viding high bandwidth access to the core. the first block is the l1 instruction memory, consisting of 32k bytes sram. this memory is accessed at full processor speed. the second core-accessible memo ry block is the l1 data mem- ory, consisting of 32k bytes. this memory block is accessed at full processor speed. the third memory block is a 4k byte l1 scratchpad sram, which runs at the same speed as the other l1 memories. l1 utility rom the l1 instruction rom contains utility rom code. this includes the tmk (vdk core), c run-time libraries, and dsp libraries. see the visualds p++ documentation for more information. custom rom (optional) the on-chip l1 instruction ro m on the adsp-bf592 may be customized to contain user code with the following features: ? 64k bytes of l1 instruction rom available for custom code ? ability to restrict access to a ll or specific segments of the on-chip rom customers wishing to customiz e the on-chip rom for their own application needs should co ntact adi sales for more infor- mation on terms and conditions and details on the technical implementation. i/o memory space the processor does not define a separate i/o space. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control registers mapped into memory-mapped registers (mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks, one which contains the control mmrs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. booting from rom the processor contains a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. if the processor is configured to boot from boot rom memory space, the proces- sor starts executing from the on-chip boot rom. for more information, see booting modes on page 11 . event handling the event controller on the proc essor handles all asynchronous and synchronous events to th e processor. the processor provides event handling that su pports both nestin g and prioriti- zation. nesting allows multiple event service routines to be active simultaneously. prioritization ensures that servicing of a higher-priority event takes preced ence over servicing of a lower- priority event. the controller prov ides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? nonmaskable interrupt (nmi ) C the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. figure 3. internal/external memory map 0x0000 0000 0xef00 0000 0xff80 0000 0xff80 8000 0xffa0 0000 0xffa0 8000 0xffa1 0000 0xffa2 0000 0xffb0 0000 0xffb0 1000 0xffc0 0000 0xffe0 0000 boot rom (4k bytes) reserved l1 instruction rom (64k bytes) reserved l1 scratchpad ram (4k bytes) reserved system memory mapped registers (2m bytes) core memory mapped registers (2m bytes) reserved data sram (32k bytes) reserved l1 instruction bank b sram (16k bytes) reserved 0xef00 1000 0xffff ffff l1 instruction bank a sram (16k bytes) 0xffa0 4000
rev. b | page 6 of 44 | july 2013 adsp-bf592 ? exceptions C events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by inpu t signals, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return-from-event instruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the processor event controller cons ists of two stages: the core event controller (cec) and the system interrupt controller (sic). the core event controller works with the system interrupt controller to prioritize and cont rol all system events. conceptu- ally, interrupts from the peripher als enter into the sic and are then routed directly into the ge neral-purpose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupt s, the two lowest priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers, leav ing seven prioritized interrupt inputs to support the peripherals of the processor. the inputs to the cec, their names in the even t vector table (evt), and their priorities are described in the adsp-bf59x blackfin processor hardware reference , system interrupts chapter. system interrupt controller (sic) the system interrupt controller provides the mapping and rout- ing of events from the many peri pheral interrupt sources to the prioritized general-purpose in terrupt inputs of the cec. although the processor provides a default mapping, the user can alter the mappings and prioriti es of interrupt events by writ- ing the appropriate values into the interrupt assignment registers (sic_iarx). the inputs into the sic and the default mappings into the cec are described in the adsp-bf59x black- fin processor hardware reference , system interrupts chapter. the sic allows further control of event processing by providing three pairs of 32-bit interrupt cont rol and status re gisters. each register contains a bit, corresponding to each peripheral inter- rupt event. for more information, see the adsp-bf59x blackfin processor hardware reference , system interrupts chapter. dma controllers the processor has multiple, in dependent dma channels that support automated data transfer s with minimal overhead for the processor core. dma transf ers can occur between the pro- cessors internal memories and any of its dma-capable peripherals. dma-capable periph erals include the sports, spi ports, uart, and ppi. each in dividual dma-capable periph- eral has at least one dedicated dma channel. the processor dma controller su pports both one-dimensional (1-d) and two-dimensional (2-d) dma transfers. dma trans- fer initialization can be implemented from registers or from sets of parameters called descriptor blocks. the 2-d dma capability support s arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 32k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video appl ications where data can be de- interleaved on the fly. examples of dma types support ed by the processor dma con- troller include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a li nked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, there are two memory dma channels, whic h are provided for transfers between the various memories of the processor system with minimal processor intervention. memory dma transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. processor peripherals the adsp-bf592 processo r contains a rich set of peripherals connected to the core via severa l high bandwidth buses, provid- ing flexibility in system configuration, as well as excellent overall system performance (see figure 1 ). the processor also contains dedicated communication modules and high speed serial and parallel ports, an inte rrupt controller for flexible man- agement of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteri stics of the processor and sys- tem to many application scenarios. the sports, spis, uart, and ppi peripherals are supported by a flexible dma structure. th ere are also separate memory dma channels dedicated to data transfers between the proces- sors various memory spaces, in cluding boot rom. multiple on-chip buses running at up to 100 mhz provide enough band- width to keep the processor core running along with activity on all of the on-chip and external peripherals. the adsp-bf592 processor includes an interface to an off-chip voltage regulator in support of the processors dynamic power management capability. watchdog timer the processor includes a 32-bit timer that can be used to imple- ment a software watchdog function. a software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (nmi), or general-pu rpose interrupt, if the timer expires before being reset by software. the programmer
adsp-bf592 rev. b | page 7 of 44 | july 2013 initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the pro- grammed value. this protects the system from remaining in an unknown state where software, wh ich would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hardware reset, the watchdog timer resets both the core and the proc essor peripherals. after a reset, software can determine whether the watchdog was the source of the hardware reset by interrogatin g a status bit in the watchdog timer control register. the timer is clocked by the system clock (sclk) at a maximum frequency of f sclk . timers there are four general-purpose programmable timer units in the processor. three timers have an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be synchronized to an external clock input to the sev- eral other associated pf pins, to an external clock input to the ppi_clk input pin, or to the internal sclk. the timer units can be used in conjunction with the uart to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timers can generate interrupt s to the processor core provid- ing periodic events for synchron ization, either to the system clock or to a count of external signals. in addition to the three general-purpose programmable timers, a fourth timer is also provided. th is extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. serial ports the adsp-bf592 processor incorporates two dual-channel synchronous serial ports (sport 0 and sport1) for serial and multiprocessor communications. the sports support the fol- lowing features: serial port data can be automa tically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to provide tdm support. in this configura- tion, one sport provides two transmit signals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ? multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ?left-justified mode serial peripheral interface (spi) ports the processor has two spi-compat ible ports that enable the processor to communicate with multiple spi-compatible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosi, and master input- slave output, miso) and a clock pi n (serial clock, sck). an spi chip select input pin (spix_ss ) lets other spi devices select the processor, and many spi chip select output pins (spix_sel7C1 ) let the processor select other spi devices. the spi select pins are reconfigured general-purpose i/ o pins. using these pins, the spi port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. uart port the adsp-bf592 processor provid es a full-duplex universal asynchronous receiver/transmitter (uart) port, which is fully compatible with pc-standard uarts. the uart port provides a simplified uart interface to other peripherals or hosts, supporting full-duplex, dma-supp orted, asynchronous trans- fers of serial data. the uart po rt includes support for five to eight data bits, one or two stop bits, and none, even, or odd par- ity. the uart port support s two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. parallel peripheral interface (ppi) the processor provides a parallel peripheral interface (ppi) that can connect directly to parallel analog-to-digital and digital-to- analog converters, video encoders and decoders, and other gen- eral-purpose peripherals. the ppi consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. the input clock supports parallel data rates up to half the system clock rate, and the synchronization signals can be configured as either inputs or outputs. the ppi supports a variety of general-purpose and itu-r 656 modes of operation. in general-purpose mode, the ppi provides half-duplex, bidirectional data transfer with up to 16 bits of data. up to three frame synchronization signals are also pro- vided. in itu-r 656 mode, th e ppi provides half-duplex bidirectional transfer of 8- or 10-bit video data. additionally, on-chip decode of embedded start-of-line (sol) and start-of- field (sof) preamble packets is supported.
rev. b | page 8 of 44 | july 2013 adsp-bf592 general-purpose mode descriptions the general-purpose modes of th e ppi are intended to suit a wide variety of data capture and transmission applications. three distinct submodes are supported: ? input mode C frame syncs and data are inputs into the ppi. input mode is intended for adc applications, as well as video communication with hardware signaling. ? frame capture mode C frame syncs are outputs from the ppi, but data are inputs. this mode allows the video source(s) to act as a slave (f or frame capture for example). ? output mode C frame syncs an d data are outputs from the ppi. output mode is used for transmitting video or other data with up to three output frame syncs. itu-r 656 mode descriptions the itu-r 656 modes of the ppi ar e intended to suit a wide variety of video capture, proce ssing, and transmission applica- tions. three distinct submodes are supported: ? active video only mode C active video only mode is used when only the active video port ion of a field is of interest and not any of the blanking intervals. ? vertical blanking only mode C in this mode, the ppi only transfers vertical blanking interval (vbi) data. ? entire field mode C in this mode, the entire incoming bit stream is read in through the ppi. twi controller interface the processor includes a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi is fu nctionally compatible with the widely used i 2 c ? bus standard. the twi module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitra- tion. the twi interface utilizes two pins for transferring clock (scl) and data (sda) and supports the protocol at speeds up to 400k bits/sec. the twi module is compatible wi th serial camera control bus (sccb) functionality for easier control of various cmos cam- era sensor devices. ports the processor groups the many peripheral signals to two portsport f and port g. most of the associated pins are shared by multiple signals. the ports fu nction as multiplexer controls. general-purpose i/o (gpio) the processor has 32 bidirectional, general-purpose i/o (gpio) pins allocated across two separate gpio modulesportfio and portgio, associated with port f and port g respectively. each gpio-capable pin shares functionality with other proces- sor peripherals via a multiplexing scheme; however, the gpio functionality is the default state of the device upon power-up. neither gpio output nor input drivers are active by default. each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers. dynamic power management the processor provides five oper ating modes, each with a differ- ent performance/power profile. in addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissi- pation. when configured for a 0 v core supply voltage, the processor enters the hibernate stat e. control of clocking to each of the processor peripherals al so reduces power consumption. see table 2 for a summary of the powe r settings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate dynamic power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. dma access is available to appropriately configured l1 memories. for more information about pll controls, see the dynamic power management chapter in the adsp-bf59x blackfin pro- cessor hardware reference . sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally, an external event wakes up the processor. system dma access to l1 me mory is not supported in sleep mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the proc essor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals may still be running but cannot access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchro- nous interrupt generated by a gpio pin. table 2. power settings mode/state pll pll bypassed core clock (cclk) system clock (sclk) core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
adsp-bf592 rev. b | page 9 of 44 | july 2013 note that when a gpio pin is us ed to trigger wake from deep sleep, the programmed wake level must linger for at least 10ns to guarantee detection. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling clocks to the processor core (ccl k) and to all of the peripherals (sclk), as well as signaling an external voltage regulator that v ddint can be shut off. any critical information stored inter- nally (for example, memory co ntents, register contents, and other information) must be written to a nonvolatile storage device prior to removing power if the processor state is to be preserved. writing b#0 to the hibernate bit causes ext_wake to transition low, wh ich can be used to signal an external voltage regu lator to shut down. since v ddext can still be supplied in this mode, all of the exter- nal pins three-state, unless othe rwise specified. this allows other devices that may be connect ed to the processor to still have power applied without drawing unwanted current. as long as v ddext is applied, the vr_ctl register maintains its state during hibernation. all other internal registers and memo- ries, however, lose their content in the hibernate state. power savings as shown in table 3 , the processor supports two different power domains, which maximizes flexibility while maintaining compliance with industry standa rds and conventions. by isolat- ing the internal logic of the processor into its own power domain, separate from other i/o, the processor can take advan- tage of dynamic power management without affecting the other i/o devices. there are no sequ encing requirements for the various power domains, but a ll domains must be powered according to the appropriate specifications table for processor operating conditions, even if the feature/peripheral is not used. the dynamic power management feature of the processor allows both the processors input voltage (v ddint ) and clock fre- quency (f cclk ) to be dynamically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynami c power dissipation by more than 40%. further, these power sa vings are additive, in that if the clock frequency and supply vo ltage are both reduced, the power savings can be dramatic, as shown in the following equations. where: f cclknom is the nominal core clock frequency f cclkred is the reduced core clock frequency v ddintnom is the nominal internal supply voltage v ddintred is the reduced internal supply voltage t nom is the duration running at f cclknom t red is the duration running at f cclkred voltage regulation the adsp-bf592 processor requires an external voltage regula- tor to power the v ddint domain. to reduce standby power consumption, the external voltage regulator can be signaled through ext_wake to remove power from the processor core. this signal is high-true for power-up and may be connected directly to the low-true shut -down input of many common regulators. while in the hibernate state, the external supply, v ddext , can still be applied, eliminating th e need for external buffers. the external voltage regulator can be activated from this power- down state by asserting the reset pin, which then initiates a boot sequence. ext_wake indicates a wakeup to the external voltage regulator. the power good (pg ) input signal allows the processor to start only after the internal voltage has reached a chosen level. in this way, the startup time of the external regulator is detected after hibernation. for a complete description of the power-good functionality, refer to the adsp-bf59x blackfin processor hard- ware reference . clock signals the processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl-compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the proce ssor includes an on-chip oscilla- tor circuit, an external crysta l may be used. for fundamental frequency operation, use the circuit shown in figure 4 . a parallel-resonant, fundamenta l frequency, microprocessor- grade crystal is connected across the clkin and xtal pins. the on-chip resistance between clkin and the xtal pin is in the 500 k range. further parallel resistors are typically not table 3. power domains power domain v dd range all internal logic and memories v ddint all other i/o v ddext power savings factor f cclkred f cclknom ------------------- - v ddintred v ddintnom ------------------------ ?? ?? 2 ? t red t nom ----------- - ? ? ? ? ? = % power savings 1 power savings factor ? ?? 100% ? =
rev. b | page 10 of 44 | july 2013 adsp-bf592 recommended. the two capacitors and the series resistor shown in figure 4 fine tune phase and amplitude of the sine frequency. the capacitor and resist or values shown in figure 4 are typical values only. the capaci tor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufactur er. the user should verify the customized values based on care ful investigations on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in figure 4 . a design procedure fo r third-overtone oper- ation is discussed in detail in (ee-168) using third overtone crystals with the adsp-218x dsp on the analog devices web- site ( www.analog.com )use site search on ee-168. the blackfin core runs at a different clock rate than the on-chip peripherals. as shown in figure 5 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a programmab le 5 to 64 multiplication factor (bounded by specified minimum and maximum vco frequencies). the default multiplier is 6, but it can be modified by a software inst ruction sequence. on-the-fly frequency changes can be effected by simply writing to the pll_div register. the maximum allowed cclk and sclk rates depend on the applied voltages v ddint and v ddext ; the vco is always permitted to run up to the frequency speci- fied by the parts instruction rate. the extclk pin can be configured to output either th e sclk frequency or the input buffered clkin frequency, called clkbuf. when configured to output sclk (clkout), the extclk pin acts as a refer- ence signal in many timing specifications. while three-stated by default, it can be enabled using the vrctl register. all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div register. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 4 illustrates typical system clock ratios. note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 5 . this programmable core cloc k capability is useful for fast core frequency modifications. the maximum cclk frequency both depends on the parts instruction rate (see ordering guide ) and depends on the applied v ddint voltage. see table 8 for details. the maximal sys- tem clock rate (sclk) depends on the chip package and the applied v ddint and v ddext voltages (see table 10 ). figure 4. external crystal connections clkin clkout (sclk) xtal select clkbuf to pll circuitry for overtone operation only: note: values marked with * must be customized, depending on the crystal and layout. please analyze carefully. for frequencies above 33 mhz, the suggested capacitor value of 18 pf should be treated as a maximum, and the suggested resistor value should be reduced to 0 . 18 pf * en 18 pf * 330 * blackfin 560 extclk en figure 5. freuency mo dification metods table 4. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0010 2:1 100 50 0110 6:1 300 50 1010 10:1 400 40 table 5. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25 pll 5 u to 64 u 1 to 15 1, 2, 4, 8 vco clkin fine adjustment requires pll sequencing coarse adjustment on-the-fly cclk sclk sclk d cclk
adsp-bf592 rev. b | page 11 of 44 | july 2013 booting modes the processor has several mechanisms (listed in table 6 ) for automatically loading internal and external memory after a reset. the boot mode is defined by the bmode input pins dedi- cated to this purpose. there are two categories of boot modes. in master boot modes, the processor acti vely loads data from parallel or serial memories. in slave boot modes, the processor receives data from ex ternal host devices. the boot modes listed in table 6 provide a number of mecha- nisms for automatically loading the proce ssors internal and external memories after a reset. by default, all boot modes use the slowest meaningful configuration settings. default settings can be altered via the initialization code feature at boot time. the bmode pins of the reset configuration register, sampled during power-on resets and so ftware-initiated resets, imple- ment the modes shown in table 6 . ? idle state/no boot (bmode - 0x0) in this mode, the boot kernel transitions the pr ocessor into idle state. the processor can then be controlled through jtag for recov- ery, debug, or other functions. ? spi1 master boot from flash (bmode = 0x2) in this mode, spi1 is configured to op erate in master mode and to connect to 8-, 16-, 24-, or 32- bit addressable devices. the processor uses the pg11/spi1_ssel5 to select a single spi eeprom/flash device, submits a read command and suc- cessive address bytes (000) un til a valid 8-, 16-, 24-, or 32- bit addressable device is detected, and begins clocking data into the processor. pull-up re sistors are required on the ssel and miso pins. by default, a value of 085 is written to the spi_baud register. ? spi1 slave boot from external master (bmode = 0x3) in this mode, spi1 is configured to operate in slave mode and to receive the bytes of the .ld r file from a spi host (mas- ter) agent. to hold off the host device from transmitting while the boot rom is busy, the blackfin processor asserts a gpio pin, called host wait (hwait), to signal to the host device not to send any more bytes until the pin is deas- serted. the host must inte rrogate the hwait signal, available on pg4, before transm itting every data unit to the processor. a pull-up resistor is required on the spi1_ss input. a pull-down on the seri al clock may improve signal quality and boot ing robustness. ? spi0 master boot from flas h (bmode = 0x4) in this mode spi0 is configured to op erate in master mode and to connect to 8-, 16-, 24-, or 32-b it addressable devices. the processor uses the pf8/spi0_ssel2 to select a single spi eeprom/flash device, submits a read command and suc- cessive address bytes (000) until a valid 8-, 16-, 24-, or 32- bit addressable device is detected, and begins clocking data into the processor. pull-up re sistors are required on the ssel and miso pins. by default, a value of 085 is written to the spi_baud register. ? boot from ppi host device (bmode = 0x5) the proces- sor operates in ppi slave mode and is configured to receive the bytes of the ldr file from a ppi host (master) agent. ? boot from uart host device (bmode = 0x6) in this mode uart0 is used as the booting source. using an auto- baud handshake sequence, a boot-stream formatted program is downloaded by the host. the host selects a bit rate within the uart clocking capabilities. when per- forming the autobaud, the uart expects a @ (040) character (eight bits data, one start bit, one stop bit, no par- ity bit) on the rxd pin to determine the bit rate. the uart then replies with an acknowledgment which is com- posed of 4 bytes (0xbfth e value of uart_dll) and (000the value of uart_dlh). the host can then download the boot stream. to hold off the host the proces- sor signals the host with th e boot host wait (hwait) signal. therefore, the host must monitor the hwait, (on pg4), before every transmitted byte. ? execute from internal l1 rom (bmode = 0x7) in this mode the processor begins ex ecution from the on-chip 64k byte l1 instruction rom star ting at address 0xffa1 0000. for each of the boot modes (exc ept execute from internal l1 rom), a 16 byte header is first brought in from an external device. the header specifies the number of bytes to be trans- ferred and the memory destinat ion address. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, program exec ution commences from the start of l1 instruction sram. the boot kernel differentiates be tween a regular hardware reset and a wakeup-from-hibernate even t to speed up booting in the latter case. bits 7C4 in the sy stem reset configuration (syscr) register can be used to bypass the boot kernel or simulate a wakeup-from-hibernate boot in case of a software reset. the boot process can be further customized by initialization code. this is a piece of code that is loaded and executed prior to the regular application boot. typically, this is used to speed up booting by managing the pll, cl ock frequencies, or serial bit rates. the boot rom also features c-callable functions that can be called by the user application at run time. this enables second stage boot or boot management schemes to be implemented with ease. table 6. booting modes bmode2C0 description 000 idle/no boot 001 reserved 010 spi1 master boot from flash, using spi1_ssel5 on pg11 011 spi1 slave boot from external master 100 spi0 master boot from flash, using spi0_ssel2 on pf8 101 boot from ppi port 110 boot from uart host device 111 execute from internal l1 rom
rev. b | page 12 of 44 | july 2013 adsp-bf592 instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax desi gned for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction in structions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/a pplication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offers the following advantages: ? seamlessly integrated dsp/mcu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools analog devices supports its proce ssors with a complete line of software and hardware development tools, including integrated development environments (which include crosscore ? embed- ded studio and/or visualdsp++ ? ), evaluation products, emulators, and a wide vari ety of software add-ins. integrated development environments (ides) for c/c++ software writing and editing, code generation, and debug support, analog devices offers two ides. the newest ide, crosscore embe dded studio, is based on the eclipse tm framework. supporting most analog devices proces- sor families, it is the ide of choice for future processors, including multicore devices. crosscore embedded studio seamlessly integrates available software add-ins to support real time operating systems, file systems, tcp/ip stacks, usb stacks, algorithmic software modules, and evaluation hardware board support packages. for more information, visit www.analog.com/cces . the other analog devices ide, visualdsp++, supports proces- sor families introduced prior to the release of crosscore embedded studio. this ide includes the analog devices vdk real time operating system and an open source tcp/ip stack. for more information visit www.analog.com/visualdsp . note that visualdsp++ will not suppo rt future analog devices processors. ez-kit lite evaluation board for processor evaluation, analog devices provides wide range of ez-kit lite ? evaluation boards. incl uding the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. also available are various ez-extenders ? , which are daughter cards delivering additional specialized functionality, including audio and video processing. for more information visit www.analog.com and search on ezkit or ezextender. ez-kit lite evaluation kits for a cost-effective way to lear n more about developing with analog devices processors, analog devices offer a range of ez- kit lite evaluation kits. each evaluation kit includes an ez-kit lite evaluation board, directions for downloading an evaluation version of the available ide(s), a usb cable, and a power supply. the usb controller on the ez-kit lite board connects to the usb port of the users pc, enab ling the chosen ide evaluation suite to emulate the on-board pr ocessor in-circuit. this permits the customer to download, execut e, and debug programs for the ez-kit lite system. it also su pports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operation. with the full version of cross- core embedded studio or visualdsp++ installed (sold separately), engineers can deve lop software for supported ez- kits or any custom system util izing supported analog devices processors. software add-ins for crosscore embedded studio analog devices offers software add-ins which seamlessly inte- grate with crosscore embedded stud io to extend its capabilities and reduce development time. add-ins include board support packages for evaluation hardwa re, various middleware pack- ages, and algorithmic modules. documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through th e crosscore embedded studio ide once the add-in is installed. board support packages for evaluation hardware software support for the ez-kit lite evaluation boards and ez- extender daughter cards is prov ided by software add-ins called board support packages (bsps). the bsps contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. a downlo ad link for a specific bsp is located on the web page for th e associated ez-kit or ez- extender product. the link is found in the product download area of the product web page.
adsp-bf592 rev. b | page 13 of 44 | july 2013 middleware packages analog devices separately offers middleware add-ins such as real time operating systems, file systems, usb stacks, and tcp/ip stacks. for more information see the following web pages: ? www.analog.com/ucos3 ? www.analog.com/ucfs ? www.analog.com/ucusbd ? www.analog.com/lwip algorithmic modules to speed development, analog de vices offers add-ins that per- form popular audio and video processing algorithms. these are available for use with both cr osscore embedded studio and visualdsp++. for more information visit www.analog.com and search on blackfin software modules or sharc software modules. designing an emulator-compatible dsp board (target) for embedded system test and de bug, analog devices provides a family of emulators. on each jtag dsp, analog devices sup- plies an ieee 1149.1 jtag test access port (tap). in-circuit emulation is facilitated by use of this jtag interface. the emu- lator accesses the processors internal features via the processors tap, allowing the de veloper to load code, set break- points, and view variables, memory, and registers. the processor must be halted to se nd data and commands, but once an operation is completed by the emulator, the dsp system is set to run at full speed with no im pact on system timing. the emu- lators require the target board to include a header that supports connection of the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the engineer-to-engineer note analog devices jtag emulation technical reference (ee-68) on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvemen ts to emulator support. additional information the following publications that describe the adsp-bf592 pro- cessor (and related processors) ca n be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf59x blackfin processor hardware reference ? blackfin processor programming reference ? adsp-bf592 blackfin processor anomaly list related signal chains a signal chain is a series of signal co nditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the circuits from the lab tm site ( www.analog.com\circuits ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques
rev. b | page 14 of 44 | july 2013 adsp-bf592 signal descriptions signal definitions for the adsp -bf592 processor are listed in table 7 . in order to maintain ma ximum function and reduce package size and pin count, some pins have dual, multiplexed functions. in cases where pin fu nction is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. during and immediately after re set, all processor signals are three-stated with the following exceptions: ext_wake is driven high and xtal is driven in conjunction with clkin to create a crystal oscillator circuit. during hibernate, all signals are three-stated with the follo wing exceptions: ext_wake is driven low and xtal is driven to a solid logic level. during and immediately after reset, all i/o pins have their input buffers disabled with the exception of the pins that need pull- ups or pull-downs, as noted in table 7 . adding a parallel termination to extclk may prove useful in further enhancing signal integrit y. be sure to verify over- shoot/undershoot and signal integrity specifications on actual hardware. table 7. signal descriptions signal name type function driver type port f: gpio and multiplexed peripherals pf0Cgpio/ dr1sec / ppi_d8 / waken1 i/o gpio/ sport1 receive data secondary / ppi data 8 / wake enable 1 a pf1Cgpio/ dr1pri / ppi_d9 i/o gpio/ sport1 receive data primary / ppi data 9 a pf2Cgpio/ rsclk1 / ppi_d10 i/o gpio/ sport1 receive serial clock / ppi data 10 a pf3Cgpio/ rfs1 / ppi_d11 i/o gpio/ sport1 receive frame sync / ppi data 11 a pf4Cgpio/ dt1sec / ppi_d12 i/o gpio/ sport1 transmit data secondary / ppi data 12 a pf5Cgpio/ dt1pri / ppi_d13 i/o gpio/ sport1 transmit data primary / ppi data 13 a pf6Cgpio/ tsclk1 / ppi_d14 i/o gpio/ sport1 transmit serial clock / ppi data 14 a pf7Cgpio/ tfs1 / ppi_d15 i/o gpio/ sport1 transmit frame sync / ppi data 15 a pf8Cgpio/ tmr2 / spi0_ssel2 / waken0 i/o gpio/ timer 2/spi0 slave select enable 2 / wake enable 0 a pf9Cgpio/ tmr0 / ppi_fs1 /spi0_ssel3 i/o gpio/ timer 0 / ppi frame sync 1 / spi0 slave select enable 3 a pf10Cgpio/ tmr1 / ppi_fs2 i/o gpio/ timer 1 / ppi frame sync 2 a pf11Cgpio/ ua_tx / spi0_ssel4 i/o gpio/ uart transmit / spi0 slave select enable 4 a pf12Cgpio/ ua_rx / spi0_ssel7 / taci2C0 i/o gpio/ uart receive / spi0 slave select enable 7 / timers 2C0 alternate input capture a pf13Cgpio/ spi0_mosi / spi1_ssel3 i/o gpio/ spi0 master out slave in / spi1 slave select enable 3 a pf14Cgpio/ spi0_miso / spi1_ssel4 i/o gpio/ spi0 master in slave out / spi1 slave select enable 4 (this pin should always be pulled high through a 4.7 k resistor, if booting via the spi port.) a pf15Cgpio/ spi0_sck / spi1_ssel5 i/o gpio/ spi0 clock / spi1 slave select enable 5 a port g: gpio and multiplexed peripherals pg0Cgpio/ dr0sec / spi0_ssel1 / spi0_ss i/o gpio/ sport0 receive data secondary / spi0 slave select enable 1 / spi0 slave select input a pg1Cgpio/ dr0pri / spi1_ssel1 / waken3 i/o gpio/ sport0 receive data primary / spi1 slave select enable 1 / wake enable 3 a pg2Cgpio/ rsclk0 / spi0_ssel5 i/o gpio/ sport0 receive serial clock / spi0 slave select enable 5 a pg3Cgpio/ rfs0 / ppi_fs3 i/o gpio/ sport0 receive frame sync / ppi frame sync 3 a pg4Cgpio(hwait)/ dt0sec / spi0_ssel6 i/o gpio (hwait output for slave boot modes)/ sport0 transmit data secondary / spi0 slave select enable 6 a pg5Cgpio/ dt0pri / spi1_ssel6 i/o gpio/ sport0 transmit data primary / spi1 slave select enable 6 a pg6Cgpio/ tsclk0 i/o gpio/ sport0 transmit serial clock a pg7Cgpio/ tfs0 / spi1_ssel7 i/o gpio/ sport0 transmit frame sync / spi1 slave select enable 7 a pg8Cgpio/ spi1_sck / ppi_d0 i/o gpio/ spi1 clock / ppi data 0 a pg9Cgpio/ spi1_mosi / ppi_d1 i/o gpio/ spi1 master out slave in / ppi data 1 a
adsp-bf592 rev. b | page 15 of 44 | july 2013 pg10Cgpio/ spi1_miso / ppi_d2 i/o gpio/ spi1 master in slave out / ppi data 2 (this pin should always be pulled high through a 4.7 k resistor if booting via the spi port.) a pg11Cgpio/ spi1_ssel5 / ppi_d3 i/o gpio/ spi1 slave select enable 5 / ppi data 3 a pg12Cgpio/ spi1_ssel2 / ppi_d4 / waken2 i/o gpio/ spi1 slave select enable 2 output / ppi data 4 / wake enable 2 a pg13Cgpio/ spi1_ssel1 / spi1_ss / ppi_d5 i/o gpio/ spi1 slave select enable 1 output / ppi data 5 / spi1 slave select input a pg14Cgpio/ spi1_ssel4 / ppi_d6 / taclk1 i/o gpio/ spi1 slave select enable 4 / ppi data 6 / timer 1 auxiliary clock input a pg15Cgpio/ spi1_ssel6 / ppi_d7 / taclk2 i/o gpio/ spi1 slave select enable 6 / ppi data 7 / timer 2 auxiliary clock input a twi scl i/o twi serial clock (this signal is an open-drain output and requires a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value.) b sda i/o twi serial data (this signal is an open-drain output and requires a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value.) b jtag port tck i jtag clk tdo o jtag serial data out a tdi i jtag serial data in tms i jtag mode select trst ijtagreset (this lead should be pulled low if the jtag port is not used.) emu o emulation output a clock clkin i clk/crystal in xtal o crystal output extclk o external clock output pin/system clock output c mode controls reset i reset nmi i nonmaskable interrupt (thisleadshouldbepulledhighwhennotused.) bmode2C0 i boot mode strap 2C0 ppi_clk i ppi clock input external regulator control pg i power good indication ext_wake o wake up indication a power supplies all supplies must be powered see operating conditions on page 16 . v ddext pi/opowersupply v ddint p internal power supply gnd g ground for all supplies (back side of lfcsp package.) table 7. signal descriptions (continued) signal name type function driver type
rev. b | page 16 of 44 | july 2013 adsp-bf592 specifications specifications are subject to change without notice. operating conditions parameter conditions min nominal max unit v ddint internal supply voltage non-automotive models 1.1 1.47 v internal supply voltage automotive models 1.33 1.47 v v ddext external supply voltage non-automotive models 1.7 1.8/2.5/3.3 3.6 v external supply voltage automotive models 2.7 3.6 v v ih high level input voltage 1, 2 1 bidirectional leads (pf15C0, pg15C0) and input leads (tck, tdi, tms, trst , clkin, reset , nmi , and bmode2C0) of the adsp-bf59 2 processor are 3.3 v tolerant (always accept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 2 parameter value applies to all input and bidirectional leads, except sda and scl. v ddext = 1.9 v 1.1 v v ihclkin high level input voltage 1, 2 v ddext = 1.9 v 1.2 v v ih high level input voltage 1, 2 v ddext = 2.75 v 1.7 v v ih high level input voltage 1, 2 v ddext = 3.6 v 2.0 v v ihclkin high level input voltage 1, 2 v ddext = 3.6 v 2.2 v v ihtwi high level input voltage 3 3 parameter applies to sda and scl. v ddext = 1.90 v/2.75 v/3.6 v 0.7 v ddext 3.6 v v il low level input voltage 1, 2 v ddext = 1.7 v 0.6 v v il low level input voltage 1, 2 v ddext = 2.25 v 0.7 v v il low level input voltage 1, 2 v ddext = 3.0 v 0.8 v v iltwi low level input voltage 3 v ddext = minimum 0.3 v ddext v t j junction temperature 64-lead lfcsp @ t ambient = 0c to +70c 0 80 c t j junction temperature 64-lead lfcsp @ t ambient = C40c to +85c C40 +95 c t j junction temperature 64-lead lfcsp @ t ambient = C40c to +105c C40 +115 c
adsp-bf592 rev. b | page 17 of 44 | july 2013 adsp-bf592 clock related operating conditions table 8 describes the core clock timing requirements for the adsp-bf592 processor. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock and system clock (see table 10 ). table 9 describes phase-locked loop operating conditions. table 8. core clock (cclk) requirements parameter min v ddint nom v ddint max cclk frequency unit f cclk core clock frequency (all models) 1.33 v 1.400 v 400 mhz core clock frequency (industrial/commercial models) 1.16 v 1.225 v 300 mhz core clock frequency (industrial/commercial models) 1.10 v 1.150 v 250 1 mhz 1 see the ordering guide on page 44 . table 9. phase-locked l oop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency (non-automotive models) 72 instruction rate 1 mhz voltage controlled oscillator (vco) frequency (automotive models) 84 instruction rate 1 mhz 1 see the ordering guide on page 44 . table 10. maximum sclk conditions parameter 1 v ddext 1.8 v/2.5 v/3.3 v nominal unit f sclk clkout/sclk frequency (v ddint ? 1.16 v ) 100 mhz clkout/sclk frequency (v ddint <1.16 v ) 80 mhz 1 f sclk must be less than or equal to f cclk .
rev. b | page 18 of 44 | july 2013 adsp-bf592 electrical characteristics parameter test conditions min typical max unit v oh high level output voltage v ddext = 1.7 v, i oh = C0.5 ma 1.35 v v oh high level output voltage v ddext = 2.25 v, i oh = C0.5 ma 2.0 v v oh high level output voltage v ddext = 3.0 v, i oh = C0.5 ma 2.4 v v ol low level output voltage v ddext = 1.7 v/2.25 v/3.0 v, i ol = 2.0 ma 0.4 v v oltwi low level output voltage v ddext = 1.7 v/2.25 v/3.0 v, i ol =2.0ma 0.4 v v i ih high level input current 1 1 applies to input pins. v ddext =3.6 v, v in = 3.6 v 10 a i il low level input current 1 v ddext =3.6 v, v in = 0 v 10 a i ihp high level input current jtag 2 2 applies to jtag input pins (tck, tdi, tms, trst) . v ddext = 3.6 v, v in = 3.6 v 10 50 a i ozh three-state leakage current 3 3 applies to three-statable pins. v ddext = 3.6 v, v in = 3.6 v 10 a i ozhtwi three-state leakage current 4 4 applies to bidirectional pins scl and sda. v ddext =3.0 v, v in = 3.6 v 10 a i ozl three-state leakage current 3 v ddext = 3.6 v, v in = 0 v 10 a c in input capacitance 5 5 applies to all signal pins. f in = 1 mhz, t ambient = 25c, v in = 2.5 v 4 8 6 6 guaranteed, but not tested. pf i dddeepsleep 7 7 see the adsp-bf59x blackfin processor hardware reference manual for definitions of sleep, deep sl eep, and hibernate operating modes. v ddint current in deep sleep mode v ddint = 1.2 v, f cclk = 0 mhz, f sclk =0mhz, t j = 25c, asf = 0.00 0.8 ma i ddsleep v ddint current in sleep mode v ddint = 1.2 v, f sclk = 25 mhz, t j = 25c 4ma i dd-idle v ddint current in idle v ddint = 1.2 v, f cclk = 50 mhz, t j = 25c, asf = 0.35 6ma i dd-typ v ddint current v ddint = 1.3 v, f cclk = 200 mhz, t j = 25c, asf = 1.00 40 ma i dd-typ v ddint current v ddint = 1.3 v, f cclk = 300 mhz, t j = 25c, asf = 1.00 66 ma i dd-typ v ddint current v ddint = 1.4 v, f cclk = 400 mhz, t j = 25c, asf = 1.00 91 ma i ddhibernate 7 hibernate state current v ddext =3.3 v, t j = 25c, clkin = 0 mhz with voltage regulator off (v ddint = 0 v) 20 a i dddeepsleep 7 v ddint current in deep sleep mode f cclk = 0 mhz, f sclk = 0 mhz table 12 ma i ddint 8 8 see table 11 for the list of i ddint power vectors covered. v ddint current f cclk ?? 0 mhz, f sclk ? 0 mhz table 12 + ( table 13 asf) ma
adsp-bf592 rev. b | page 19 of 44 | july 2013 total power dissipation total power dissipation has two components: 1. static, including leakage current 2. dynamic, due to transistor switching characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 18 shows the current dissipation for internal circuitry (v ddint ). i dddeepsleep specifies static power dissipati on as a function of voltage (v ddint ) and temperature (see table 12 ), and i ddint specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (v ddint ) and frequency ( table 13 ). there are two parts to the dynami c component. the first part is due to transistor switching in the core clock (cclk) domain. this part is subject to an acti vity scaling factor (asf), which represents application code runn ing on the processor core and l1 memories ( table 11 ). the asf is combined with the cclk frequency and v ddint dependent data in table 13 to calculate this part. the second part is due to transistor switch ing in the system clock (sclk) domain, which is included in the i ddint specification equation. table 11. activity scaling factors (asf) 1 1 see estimating power for a sdp-bf534/bf536/bf537 blackfin processors (ee-297) . the power vector information al so applies to the adsp-bf592 processor. i ddint power vector activity scaling factor (asf) i dd-peak 1.29 i dd-high 1.26 i dd-typ 1.00 i dd-app 0.83 i dd-nop 0.66 i dd-idle 0.33 table 12. static current - i dd-deepsleep (ma) t j (c) 1 voltage (v ddint ) 1 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 1.40 v 1.45 v 1.50 v 25 0.85 0.98 1.13 1.29 1.46 1.62 1.85 2.07 40 1.57 1.8 2.012.162.512.743.053.36 55 2.57 2.88 3.2 3.5 3.84 4.22 4.63 5.05 70 4.04 4.45 4.86 5.3 5.81 6.31 6.87 7.45 85 6.52 7.12 7.73 8.36 9.09 9.86 10.67 11.54 100 9.67 10.51 11.37 12.24 13.21 14.26 15.37 16.55 115 14.18 15.29 16.45 17.71 19.05 20.45 21.96 23.56 1 valid temperature and voltage ranges are model-specific. see operating conditions on page 16 . table 13. dynamic current in cclk domain (ma, with asf = 1.0) 1 f cclk (mhz) 2 voltage (v ddint ) 2 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 1.40 v 1.45 v 1.50 v 400 n/a n/a n/a n/a 85.31 88.96 92.81 96.63 350 n/a n/a n/a 72.08 75.41 78.70 82.07 85.46 300 n/a 57.52 60.38 63.22 66.14 69.02 71.93 75.05 250 46.10 48.43 50.76 53.19 55.68 58.17 60.69 63.23 200 37.86 39.80 41.76 43.79 45.81 47.85 49.97 52.09 100 21.45 22.56 23.78 24.98 25.97 26.64 27.92 29.98 1 the values are not guaranteed as stand-al one maximum specifications. they must be combined with stat ic current per the equation s of electrical characteristics on page 18 . 2 valid frequency and voltage ra nges are model-specific. see operating conditions on page 16 and table 8 on page 17 .
rev. b | page 20 of 44 | july 2013 adsp-bf592 absolute maximum ratings stresses greater than those listed in table 14 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 14 specifies the maximum total source/sink (i oh /i ol ) cur- rent for a group of pins and for individual pins. permanent damage can occur if this value is exceeded. to understand this specification, if pins pf0 and pf1 from group 1 in table 16 were sourcing or sinking 10 ma each, the total current for those pins would be 20 ma. this woul d allow up to 35 ma total that could be sourced or sunk by th e remaining pins in the group without damaging the device. it should also be noted that the maximum source or sink current for an individual pin cannot exceed 25 ma. the list of all groups and their pins are shown in table 16 . note that the v oh and v ol specifications have separate per-pin maximum current requirements, see the electrical characteristics table. esd sensitivity table 14. absolute maximum ratings parameter rating internal supply voltage (v ddint ) C0.3 v to +1.50 v external (i/o) supply voltage (v ddext )C0.3 v to +3.8 v input voltage 1, 2 1 applies to 100% transient duty cycle. for other duty cycles see table 15 . 2 applies only when v ddext is within specif ications. when v ddext is outside speci- fications, the range is v ddext 0.2 volts. C0.5 v to +3.6 v output voltage swing C0.5 v to v ddext +0.5 v i oh /i ol current per pin group 55 ma (max) i oh /i ol current per individual pin 25 ma (max) storage temperature range C65c to +150c junction temperature while biased (non-automotive models) +110c junction temperature while biased (automotive models) +115c table 15. maximum duty cycle for input transient voltage 1 1 applies to all signal pins with th e exception of clkin, xtal, ext_wake. v in min (v) 2 2 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case observed value must fall within one of the voltages specified, and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less th an or equal to the corresponding duty cycle. v in max (v) 2 maximum duty cycle 3 3 duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. the is equivalent to the meas ured duration of a single instance of overshoot or unders hoot as a percentage of the period of occurrence. C0.5 +3.8 100% C0.7 +4.0 40% C0.8 +4.1 25% C0.9 +4.2 15% C1.0 +4.3 10% table 16. total current pin groupsCv ddext groups group pins in group 1 pf0, pf1, pf2, pf3 2 pf4, pf5, pf6, pf7 3 pf8, pf9, pf10, pf11 4 pf12, pf13, pf14, pf15 5 pg3, pg2, pg1, pg0 6 pg7, pg6, pg5, pg4 7 pg11, pg10, pg9, pg8 8 pg15, pg14, pg13, pg12 9 tdi, tdo, emu, tck, trst , tms 10 bmode2, bmode1, bmode0 11 ext_wake, pg , reset , nmi , ppi_clk, extclk 12 sda, scl, clkin, xtal esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality.
adsp-bf592 rev. b | page 21 of 44 | july 2013 package information the information presented in figure 6 and table 17 provides details about the package brandi ng for the adsp-bf592 proces- sor. for a complete listing of product availability, see ordering guide on page 44 . figure 6. product information on package table 17. package br and information brand key field description adsp-bf592 product name t temperature range pp package type z rohs compliant designation ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliance designator yyww date code vvvvvv.x n.n tppzccc adsp-bf592 a #yyww country_of_origin b
rev. b | page 22 of 44 | july 2013 adsp-bf592 timing specifications specifications are subject to change without notice. clock and reset timing table 18 and figure 7 describe clock and reset operations. per the cclk and sclk timing specifications in table 8 to table 10 , combinations of clkin and clock multipliers must not select core/peripheral clocks in excess of the processors instruction rate. table 18. clock and reset timing v ddext 1.8 v nominal v ddext 2.5 v/3.3 v nominal parameter min max min max unit timing requirement s f ckin clkin period 1, 2, 3, 4 12 50 12 50 mhz t ckinl clkin low pulse 1 10 10 ns t ckinh clkin high pulse 1 10 10 ns t wrst reset asserted pulse width low 5 11 t ckin 11 t ckin ns switching characteristic t bufdlay clkin to clkbuf 6 delay 11 10 ns 1 applies to pll bypass mode and pll non bypass mode. 2 combinations of the clkin frequency and the p ll clock multiplier must not exceed the allowed f vco , f cclk , and f sclk settings discussed in table 8 on page 17 through table 10 on page 17 . 3 the t ckin period (see figure 7 ) equals 1/f ckin . 4 if the df bit in the pll_ctl register is set, the minimum f ckin specification is 24 mhz. 5 applies after power-up se quence is complete. see table 19 and figure 8 for power-up reset timing. 6 the adsp-bf592 processor does not have a dedicated clkbuf pin. rath er, the extclk pin may be programmed to serve as clkbuf or c lkout. this parameter applies when extclk is programmed to output clkbuf. figure 7. clock and reset timing clkin t wrst t ckin t ckinl t ckinh t bufdlay t bufdlay reset clkbuf
adsp-bf592 rev. b | page 23 of 44 | july 2013 table 19. power-up reset timing parameter min max unit timing requirement s t rst_in_pwr reset deasserted after the v ddint , v ddext , and clkin pins are stable and within specification 3500 t ckin s figure 8. power-up reset timing reset t rst_in_pwr clkin v dd_supplies
rev. b | page 24 of 44 | july 2013 adsp-bf592 parallel peripheral interface timing table 20 and figure 9 through figure 13 describe parallel peripheral interface operations. table 20. parallel peripheral interface timing parameter v ddext = 1.8 v v ddext = 2.5 v/3.3 v min max min max unit timing requirements t pclkw ppi_clk width 1 t sclk C1.5 t sclk C1.5 ns t pclk ppi_clk period 1 2 t sclk C1.5 2 t sclk C1.5 ns timing requirementsgp input and frame capture modes t psud external frame sync startup delay 2 4 t pclk 4 t pclk ns t sfspe external frame sync setup before ppi_clk (nonsampling edge for rx, sampling edge for tx) 6.7 6.7 ns t hfspe external frame sync hold after ppi_clk 1.8 1.6 ns t sdrpe receive data setup before ppi_clk 4.1 3.5 ns t hdrpe receive data hold after ppi_clk 2 1.6 ns switching characteristicsgp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 9.0 8.0 ns t hofspe internal frame sync hold after ppi_clk 1.7 1.7 ns t ddtpe transmit data delay after ppi_clk 8.7 8.0 ns t hdtpe transmit data hold after ppi_clk 2.3 1.9 ns 1 ppi_clk frequency cannot exceed f sclk /2. 2 the ppi port is fully enabled 4 ppi clock cy cles after the pab write to the ppi port en able bit. only after the ppi port is ful ly enabled are external frame syncs and data words guaranteed to be received co rrectly by the ppi peripheral. figure 9. ppi with external frame sync timing figure 10. ppi gp rx mode with external frame sync timing ppi_clk ppi_fs1/2 t psud t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw
adsp-bf592 rev. b | page 25 of 44 | july 2013 figure 11. ppi gp tx mode with external frame sync timing figure 12. ppi gp rx mode with internal frame sync timing figure 13. ppi gp tx mode wi th internal frame sync timing t hdtpe t sfspe data driven / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw t hdrpe t sdrpe t hofspe frame sync driven data sampled ppi_data ppi_clk ppi_fs1/2 t dfspe t pclk t pclkw t hofspe frame sync driven data driven ppi_data ppi_clk ppi_fs1/2 t dfspe t ddtpe t hdtpe t pclk t pclkw data driven
rev. b | page 26 of 44 | july 2013 adsp-bf592 serial ports table 21 through table 25 and figure 14 through figure 18 describe serial port operations. table 21. serial portsexternal clock parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit timing requirements t sfse tfsx/rfsx setup before tsclkx/rsclkx 1 33ns t hfse tfsx/rfsx hold after tsclkx/rsclkx 1 33ns t sdre receive data setup before rsclkx 1 33ns t hdre receive data hold after rsclkx 1 3.5 3 ns t sclkew tsclkx/rsclkx width 4.5 4.5 ns t sclke tsclkx/rsclkx period 2 t sclk 2 t sclk ns t sudte start-up delay from sport enable to first external tfsx 2 4 t tsclke 4 t tsclke ns t sudre start-up delay from sport enable to first external rfsx 2 4 t rsclke 4 t rsclke ns switching characteristics t dfse tfsx/rfsx delay after tsclkx/rsclkx (internally generated tfsx/rfsx) 3 10 10 ns t hofse tfsx/rfsx hold after tsclkx/rsclkx (internally generated tfsx/rfsx) 1 00ns t ddte transmit data delay after tsclkx 1 11 10 ns t hdte transmit data hold after tsclkx 1 00ns 1 referenced to sample edge. 2 verified in design but untested. 3 referenced to drive edge. table 22. serial portsinternal clock parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit timing requirements t sfsi tfsx/rfsx setup before tsclkx/rsclkx 1 11.5 9.6 ns t hfsi tfsx/rfsx hold after tsclkx/rsclkx 1 C1.5 C1.5 ns t sdri receive data setup before rsclkx 1 11.5 11.3 ns t hdri receive data hold after rsclkx 1 C1.5 C1.5 ns switching characteristics t sclkiw tsclkx/rsclkx width 7 8 ns t dfsi tfsx/rfsx delay after tsclkx/rsclkx (internally generated tfsx/rfsx) 2 43ns t hofsi tfsx/rfsx hold after tsclkx/rsclkx (internally generated tfsx/rfsx) 1 C2 C2 ns t ddti transmit data delay after tsclkx 1 43ns t hdti transmit data hold after tsclkx 1 C1.8 C1.5 ns 1 referenced to sample edge. 2 referenced to drive edge.
adsp-bf592 rev. b | page 27 of 44 | july 2013 figure 14. serial ports figure 15. serial port start up with external clock and frame sync t sdri rsclkx drx drive edge t hdri t sfsi t hfsi t dfsi t h ofsi t sclkiw data receiveinternal clock t sdre data receiveexternal clock rsclkx drx t hdre t sfse t hfse t dfse t sclkew t hofse t ddti t hdti tsclkx tfsx (input) dtx t sfsi t hfsi t sclkiw t dfsi t hofsi data transmitinternal clock t ddte t hdte tsclkx dtx t sfse t dfse t sclkew t hofse data transmitexternal clock sample edge drive edge sample edge drive edge sample edge drive edge sample edge t sclke t sclke t hfse tfsx (output) tfsx (input) tfsx (output) rfsx (input) rfsx (output) rfsx (input) rfsx (output) tsclkx (input) tfsx (input) rfsx (input) rsclkx (input) t sudte t sudre first tsclkx/rsclkx edge after sport enabled
rev. b | page 28 of 44 | july 2013 adsp-bf592 table 23. serial portsenable and three-state parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit switching characteristics t dtene data enable delay from external tsclkx 1 00ns t ddtte data disable delay from external tsclkx 1 t sclk + 1 t sclk + 1 ns t dteni data enable delay from internal tsclkx 1 C2 C2 ns t ddtti data disable delay from internal tsclkx 1 t sclk + 1 t sclk + 1 ns 1 referenced to drive edge. figure 16. serial ports enable and three-state tsclkx dtx drive edge t ddtte/i t dtene/i drive edge
adsp-bf592 rev. b | page 29 of 44 | july 2013 table 24. serial portsexternal late frame sync parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit switching characteristics t ddtlfse data delay from late external tfsx or external rfsx in multi-channel mode with mfd = 0 1, 2 12 10 ns t dtenlfse data enable from external rfsx in multi-channel mode with mfd = 0 1, 2 00ns 1 when in multi-channel mode, tfsx enable and tfsx valid follow t dtenlfse and t ddtlfse . 2 if external rfsx/tfsx setu p to rsclkx/tsclkx > t sclke /2 then t ddtte/i and t dtene/i apply, otherwise t ddtlfse and t dtenlfse apply. figure 17. serial ports external late frame sync rsclkx rfsx dtx drive edge drive edge sample edge external rfsx in multi-channel mode 1st bit t dtenlfse t ddtlfse tsclkx tfsx dtx drive edge drive edge sample edge late external tfsx 1st bit t ddtlfse
rev. b | page 30 of 44 | july 2013 adsp-bf592 table 25. serial portsgated clock mode v ddext 1.8v nominal v ddext 2.5 v/3.3 v nominal parameter min max min max unit timing requirements t sdri receive data setup before tsclkx 11.3 8.7 ns t hdri receive hold after tsclkx 0 0 ns switching characteristics t ddti transmit data delay after tsclkx 3 3 ns t hdti transmit data hold after tsclkx C1.8 C1.8 ns t dftsclkcnv first tsclkx edge delay after tfsx/tmr1 low 0.5 t tsclk C 3 0.5 t tsclk C 3 ns t dcnvltsclk tfsx/tmr1 high delay after last tsclkx edge t tsclk C 3 t tsclk C 3 ns figure 18. serial ports gated clock mode tsclkx (out) gated clock mode data receive tfs/tmr (out) dtx delay time data transmit t hdri t sdri tsclkx (out) tsclkx (out) t ddti t hdti drx t dftsclkcnv t dcnvltsclk t dcnvltsclk t dftsclkcnv
adsp-bf592 rev. b | page 31 of 44 | july 2013 serial peripheral interface (spi) portmaster timing table 26 and figure 19 describe spi port master operations. table 26. serial peripheral interface (spi) portmaster timing parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit timing requirements t sspidm data input valid to sck edge (data input setup) 11.6 9.6 ns t hspidm sck sampling edge to data input invalid C1.5 C1.5 ns switching characteristics t sdscim spi_selx low to first sck edge 2 t sclk C 1.5 2 t sclk C 1.5 ns t spichm serial clock high period 2 t sclk C 1.5 2 t sclk C 1.5 ns t spiclm serial clock low period 2 t sclk C 1.5 2 t sclk C 1.5 ns t spiclk serial clock period 4 t sclk C 1.5 4 t sclk C 1.5 ns t hdsm last sck edge to spi_selx high 2 t sclk C 2 2 t sclk C 1.5 ns t spitdm sequential transfer delay 2 t sclk C 1.5 2 t sclk C 1.5 ns t ddspidm sck edge to data out valid (data out delay) 0606ns t hdspidm sck edge to data out invalid (data out hold) C1 C1 ns figure 19. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spixsely (output) spixsck (output) spixmosi (output) spixmiso (input) spixmosi (output) spixmiso (input) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm
rev. b | page 32 of 44 | july 2013 adsp-bf592 serial peripheral interface (spi) portslave timing table 27 and figure 20 describe spi port slave operations. table 27. serial peripheral interface (spi) portslave timing parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit timing requirements t spichs serial clock high period 2 t sclk C 1.5 2 t sclk C 1.5 ns t spicls serial clock low period 2 t sclk C 1.5 2 t sclk C 1.5 ns t spiclk serial clock period 4 t sclk 4 t sclk ns t hds last sck edge to spi_ss not asserted 2 t sclk C 1.5 2 t sclk C 1.5 ns t spitds sequential transfer delay 2 t sclk C 1.5 2 t sclk C 1.5 ns t sdsci spi_ss assertion to first sck edge 2 t sclk C 1.5 2 t sclk C 1.5 ns t sspid data input valid to sck edge (data input setup) 1.6 1.6 ns t hspid sck sampling edge to data input invalid 2 1.6 ns switching characteristics t dsoe spi_ss assertion to data out active 0 12 0 10.3 ns t dsdhi spi_ss deassertion to data high impedance 0 11 0 9 ns t ddspid sck edge to data out valid (data out delay) 10 10 ns t hdspid sck edge to data out invalid (data out hold) 0 0 ns figure 20. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spixss (input) spixsck (input) spixmiso (output) spixmosi (input) spixmiso (output) spixmosi (input) cpha = 1 cpha = 0 t hspid
adsp-bf592 rev. b | page 33 of 44 | july 2013 universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing the uart ports receive and tran smit operations are described in the adsp-bf59x hardware reference manual . general-purpose port timing table 28 and figure 21 describe general-purpose port operations. table 28. general-purpose port timing parameter v ddext 1.8v/2.5 v/3.3v nominal min max unit timing requirement t wfi general-purpose port pin input pulse width t sclk + 1 ns switching characteristic t gpod general-purpose port pin output delay from clkout low 0 11 ns figure 21. general-purpose port timing clkout gpio output gpio input t wfi t gpod
rev. b | page 34 of 44 | july 2013 adsp-bf592 timer cycle timing table 29 and figure 22 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /2) mhz. timer clock timing table 30 and figure 23 describe timer clock timing. table 29. timer cycle timing parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit timing requirements t wl timer pulse width input low (measured in sclk cycles) 1 1 t sclk 1 t sclk ns t wh timer pulse width input high (measured in sclk cycles) 1 1 t sclk 1 t sclk ns t tis timer input setup time before clkout low 2 10 8 ns t tih timer input hold time after clkout low 2 C2 C2 ns switching characteristics t hto timer pulse width output (measured in sclk cycles) 1 t sclk C 2 (2 32 C 1) t sclk t sclk C 1.5 (2 32 C 1) t sclk ns t tod timer output update delay after clkout high 6 6 ns 1 the minimum pulse widths apply for tmrx sign als in width capture and external clock mode s. they also apply to the pg0 or ppi_cl k signals in pwm output mode. 2 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to re synchronize programmable flag in puts. figure 22. timer cycle timing clkout tmrx output tmrx input t tis t tih t wh ,t wl t tod t hto table 30. timer clock timing parameter v ddext = 1.8 v v ddext = 2.5v/3.3 v min max min max unit switching characteristic t todp timer output update delay after ppi_clk high 12.64 12.64 ns figure 23. timer clock timing ppi_clk tmrx output t todp
adsp-bf592 rev. b | page 35 of 44 | july 2013 jtag test and emulation port timing table 31 and figure 24 describe jtag port operations. table 31. jtag port timing parameter v ddext 1.8v nominal v ddext 2.5 v/3.3v nominal min max min max unit timing requirements t tck tck period 20 20 ns t stap tdi, tms setup before tck high 4 4 ns t htap tdi, tms hold after tck high 4 4 ns t ssys system inputs setup before tck high 1 45ns t hsys system inputs hold after tck high 1 55ns t trstw trst pulse width 2 (measured in tck cycles) 4 4 tck switching characteristics t dtdo tdo delay from tck low 10 10 ns t dsys system outputs delay after tck low 3 13 13 ns 1 system inputs = scl, sda, pf 15C0, pg15C0, ph2C0, tck, nmi , bmode3C0, pg . 2 50 mhz maximum. 3 system outputs = clkout, scl, sda, pf15C0, pg15C0, ph2C0, tdo, emu , ext_wake. figure 24. jtag port timing tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. b | page 36 of 44 | july 2013 adsp-bf592 output drive currents figure 25 through figure 33 show typical current-voltage char- acteristics for the output driver s of the adsp-bf592 processor. the curves represent the current drive capability of the output drivers. see table 7 on page 14 for information about which driver type corresponds to a particular pin. figure 25. driver type a current (3.3v v ddext ) figure 26. drive type a current (2.5v v ddext ) 0 source current (ma) 120 100 40 C100 C40 v ol v oh 80 C60 C80 C20 20 60 source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v ddext = 3.0v @ C 40 c v ddext = 3.3v @ 25 c v ddext = 3.6v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 80 60 20 C80 C60 C20 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 40 C40 v ddext = 2.25v @ 105 c figure 27. driver type a current (1.8v v ddext ) figure 28. driver type b current (3.3v v ddext ) figure 29. driver type b current (2.5v v ddext ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 40 30 20 C40 C30 C10 v ol v oh C20 10 v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c v ddext = 1.7v @ 105 c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 source current (ma) source voltage (v) 120 100 40 C120 C100 C40 v ol v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c 80 C60 v ddext = 3.0v @ 105 c C80 C20 20 60 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 80 60 20 C80 C60 C20 v ol v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 40 C40 v ddext = 2.25v @ 105 c
adsp-bf592 rev. b | page 37 of 44 | july 2013 test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. figure 34 shows the measurement point for ac measurements (except out- put enable/disable). the measurement point v meas is v ddext /2 for v ddext (nominal) = 1.8 v/2.5 v/3.3 v. output enable time measurement output pins are considered to be enabled when th ey have made a transition from a high impedanc e state to the po int when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of figure 35 . figure 30. driver type b current (1.8v v ddext ) figure 31. driver type c current (3.3v v ddext ) figure 32. driver type c current (2.5v v ddext ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 30 20 C30 C10 v ol v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C20 C40 10 40 v ddext = 1.7v @ 105 c 50 C50 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 90 60 C 90 C 30 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C 60 C 150 30 120 v ddext = 3.0v @ 105 c C 120 150 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 100 C 100 C 25 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c C 50 v ddext = 2.25v @ 105 c C 75 25 50 75 figure 33. driver type c current (1.8v v ddext ) figure 34. votage reference leves for ac measurements (except output enae/disae) figure 35. output enae/disae 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 60 40 C60 C20 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C40 20 v ddext = 1.7v @ 105 c input or output v meas v meas reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) v trip (high) v oh (measured ) v ol (measured) high impedance state output stops driving t ena t decay t ena_measured t trip v trip (low)
rev. b | page 38 of 44 | july 2013 adsp-bf592 the time t ena_measured is the interval from when the reference signal switches to when the output voltage reaches v trip (high) or v trip (low) and is shown below. ?v ddext (nominal) = 1.8 v, v trip (high) is 1.05 v, v trip (low) is 0.75 v ?v ddext (nominal) = 2.5 v, v trip (high) is 1.5 v, v trip (low) is 1.0 v ?v ddext (nominal) = 3.3 v, v trip (high) is 1.9 v, v trip (low) is 1.4 v time t trip is the interval from when the output starts driving to when the output reaches the v trip (high) or v trip (low) trip voltage. time t ena is calculated as shown in the equation: if multiple pins are enabled, th e measurement value is that of the first lead to start driving. output disable time measurement output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the output disable time t dis is the difference between t dis_measured and t decay as shown on the left side of figure 35 . the time for the voltage on the bus to decay by v is dependent on the capacitive load c l and the load current i l . this decay time can be approximated by the equation: the time t decay is calculated with test loads c l and i l , and with v equal to 0.25 v for v ddext (nominal) = 2.5 v/3.3 v and 0.15 v for v ddext (nominal) = 1.8v. the time t dis_measured is the interval from when the reference signal switches to when the output voltage decays v from the measured output high or output low voltage. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the processors output voltage and the input threshold for the device requiring the hold time. c l is the total bus capacitance (per data line), and i l is the total leak- age or three-state current (per data line). the hold time will be t decay plus the various output disa ble times as specified in the timing specifications on page 22 . capacitive loading output delays and holds are based on standard capacitive loads of an average of 6 pf on all pins (see figure 36 ). v load is equal to (v ddext )/2. the graphs of figure 37 through figure 42 show how output rise time varies with capacitance. the delay and hold specifica- tions given should be derated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. t ena t ena_measured t trip ? = t dis t dis_measured t decay ? = t decay c l v ? ?? i l ? = figure 36. equivalent device loading for ac measurements (includes all fixtures) figure 37. driver type a typical rise and fall times (10%C90%) vs. load capacitance (1.8v v ddext ) t1 zo = 50 : (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 : 0.5pf 70 : 400 : 45 : 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 : 8 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 18 14 0 2 6 12 200 t rise t fall t fall = 1.8v @ 25 c t rise = 1.8v @ 25 c 4 10 16 20
adsp-bf592 rev. b | page 39 of 44 | july 2013 figure 38. driver type a typical rise and fall times (10%C90%) vs. load capacitance (2.5v v ddext ) figure 39. driver type a typical rise and fall times (10%C90%) vs. load capacitance (3.3v v ddext ) figure 40. driver type c typical rise and fall times (10%C90%) vs. load capacitance (1.8v v ddext ) 8 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 18 14 0 2 6 12 200 t rise t fall t fall = 2.5v @ 25 c t rise = 2.5v @ 25 c 4 10 16 8 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 16 12 0 2 4 10 200 t rise t fall 6 14 t fall = 3.3v @ 25 c t rise = 3.3v @ 25 c 6 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 12 10 0 2 4 8 200 t rise t fall t fall = 1.8v @ 25 c t rise = 1.8v @ 25 c figure 41. driver type c typical rise and fall times (10%C90%) vs. load capacitance (2.5v v ddext ) figure 42. driver type c typical rise and fall times (10%C90%) vs. load capacitance (3.3v v ddext ) 4 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 9 7 0 1 3 6 200 t rise t fall t fall = 2.5v @ 25 c t rise = 2.5v @ 25 c 2 5 8 4 rise and fall time (ns) load capacitance (pf) 0 50 100 150 250 7 6 0 1 2 5 200 t rise t fall 3 t fall = 3.3v @ 25 c t rise = 3.3v @ 25 c
rev. b | page 40 of 44 | july 2013 adsp-bf592 environmental conditions to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature (c) t case = case temperature (c) meas ured by customer at top cen- ter of package. ? jt = from table 32 p d = power dissipation (see total power dissipation on page 19 for the method to calculate p d ) values of ? ja are provided for package comparison and printed circuit board design considerations. ? ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature (c) values of ? jc are provided for packag e comparison and printed circuit board design considerations when an external heat sink is required. values of ? jb are provided for packag e comparison and printed circuit board design considerations. in table 32 , airflow measurements comply with jedec stan- dards jesd51-2 and jesd51-6, and the junction-to-board measurement complies with je sd51-8. the junction-to-case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. table 32. thermal characteristics parameter condition typical unit ja 0 linear m/s air flow 23.5 c/w jma 1 linear m/s air flow 20.9 c/w jma 2 linear m/s air flow 20.2 c/w jb 11.2 c/w jc 9.5 c/w jt 0 linear m/s air flow 0.21 c/w jt 1 linear m/s air flow 0.36 c/w jt 2 linear m/s air flow 0.43 c/w t j t case ? jt p d ? ?? + = t j t a ? ja p d ? ?? + =
adsp-bf592 rev. b | page 41 of 44 | july 2013 64-lead lfcsp lead assignment table 33 lists the lfcsp leads by signal mnemonic. table 34 lists the lfcsp by lead number. table 33. 64-lead lfcsp lead assignment (alphabetical by signal) signal lead no. signal lead no. signal lead no. signal lead no. bmode0 29 pf7 7 pg6 38 tdo 23 bmode1 28 pf8 10 pg7 39 tms 21 bmode2 27 pf9 11 pg8 42 trst 20 extclk/sclk 57 pf10 12 pg9 43 v ddext 3 clkin61pf1113pg1044v ddext 14 emu 19 pf12 15 pg11 45 v ddext 25 ext_wake 51 pf13 16 pg12 47 v ddext 35 gnd30pf1417pg1348v ddext 46 nmi 54 pf15 18 pg14 49 v ddext 58 pf0 63 pg 52 pg15 50 v ddint 8 pf1 64 pg0 31 ppi_clk 56 v ddint 9 pf2 1 pg1 32 reset 53 v ddint 26 pf3 2 pg2 33 scl 60 v ddint 40 pf4 4 pg3 34 sda 59 v ddint 41 pf5 5 pg4 36 tck 24 v ddint 55 pf6 6 pg5 37 tdi 22 xtal 62 gnd * 65 * lead no. 65 is the gnd supply (see figure 43 and figure 44 ) for the processor (6.2 mm 6.2 mm); this pad must connect to gnd. table 34. 64-lead lfcsp lead assignment (numerical by lead number) lead no. signal lead no. signal lead no. signal lead no. signal 1 pf2 17 pf14 33 pg2 49 pg14 2 pf3 18 pf15 34 pg3 50 pg15 3v ddext 19 emu 35 v ddext 51 ext_wake 4pf420trst 36 pg4 52 pg 5 pf5 21 tms 37 pg5 53 reset 6pf622tdi38pg654nmi 7pf723tdo39pg755v ddint 8v ddint 24 tck 40 v ddint 56 ppi_clk 9v ddint 25 v ddext 41 v ddint 57 extclk/sclk 10 pf8 26 v ddint 42 pg8 58 v ddext 11pf927bmode243pg959sda 12 pf10 28 bmode1 44 pg10 60 scl 13 pf11 29 bmode0 45 pg11 61 clkin 14 v ddext 30 gnd 46 v ddext 62 xtal 15 pf12 31 pg0 47 pg12 63 pf0 16 pf13 32 pg1 48 pg13 64 pf1 65 gnd * * pin no. 65 is the gnd supply (see figure 43 and figure 44 ) for the processor (6.2 mm 6.2 mm); this pad must connect to gnd.
rev. b | page 42 of 44 | july 2013 adsp-bf592 figure 43 shows the top view of the lfcsp lead configuration. figure 44 shows the bottom view of the lfcsp lead configuration. figure 43. 64-lead lfcsp lead configuration (top view) pin 1 pin 16 pin 4 8 pin 33 pin 64 pin 49 pin 17 pin 3 2 pin 1 indicator ad s p-bf592 64-lead lfc s p top view figure 44. 64-lead lfcsp lead configuration (bottom view) pin 4 8 pin 33 pin 1 pin 16 pin 49 pin 64 pin 3 2 pin 17 pin 1 indicator ad s p-bf592 64-lead lfc s p bottom view gnd pad (pin 65)
adsp-bf592 rev. b | page 43 of 44 | july 2013 outline dimensions dimensions in figure 45 are shown in millimeters. figure 45. 64-lead lead frame chip scale package [lfcsp_vq 1 ] very thin quad (cp-64-4) dimensions shown in millimeters 1 for information relating to the cp-64-4 pack ages exposed pad, see the table endnotes on page 41 . compliant to jedec standards mo-220-vmmd-4 6.35 6.20 sq 6.05 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the lead assignment and signal descriptions sections of this data sheet.
rev. b | page 44 of 44 | july 2013 adsp-bf592 ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09574-0-7/13(b) automotive products the adsp-bf592 is available with controlled manufacturing to support the quality and re liability requirements of automotive app lica- tions. note that this automotive model may have specifications that differ from the commercial models and designers should revi ew the product specifications section of this data sheet ca refully. only the automotive grade products shown in table 35 are available for use in automotive applications. contact your local adi account representative for specific pr oduct ordering information and to obtain the spe- cific automotive reliabilit y reports for these models. ordering guide table 35. automotive products model 1 1 z = rohs compliant part. temperature range 2 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 16 for junction temperature (t j ) specification, which is the on ly temperature specification. instruction rate (max) package description package option adbf592wycpzxx C40oc to +105oc 400 mhz 64-lead lfcsp cp-64-4 model 1, 2 1 z = rohs compliant part. 2 available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. fo r a complete list, visit our website at www.analog.com /blackfin. temperature range 3 3 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 16 for junction temperature (t j ) specification, which is the on ly temperature specification. instruction rate (max) package description package option adsp-bf592kcpz-2 0oc to +70oc 200 mhz 64-lead lfcsp cp-64-4 adsp-bf592kcpz 0oc to +70oc 400 mhz 64-lead lfcsp cp-64-4 ADSP-BF592BCPZ-2 C40oc to +85oc 200 mhz 64-lead lfcsp cp-64-4 adsp-bf592bcpz C40oc to +85oc 400 mhz 64-lead lfcsp cp-64-4

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